Morteza Hosseini
PhD Candidate
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About me:
I am a PhD candidate in computer engineering. My research interests are training quantized pruned deep neural networks for large datasets, hardware accelerator design for machine learning applications, and Markov Chain Monte Carlo methods. My current research focus is on optimizing neural networks for energy-efficient implementation on hardware.
Education:
University of Maryland, Baltimore County (MD, USA) Jan2016-Present
PhD Candidate in Computer Engineering
Sharif University of Technology (Tehran, IRAN) Sep2009-Feb2012
MSc in Electrical Engineering - Digital Electronics
Iran University of Science and Technology (Tehran, IRAN) Sep2003-Sep2009
BSc in Electrical Engineering - Electronics
Conference Papers:
Morteza Hosseini, Haoran Ren, Hassib-Al Rashid, Arnab Mazumder, Bharat Prakash, and Tinoosh Mohsenin “Neural Networks for Pulmonary Disease Diagnosis using Auditory and Demographic Information” in ACM Epidemiology meets Data Mining and Knowledge discovery (EpiDAMIK) 2020
Morteza Hosseini, Hiren Paneliya, Uttej Kallakuri and Tinoosh Mohsenin "On the Complexity Reduction of Dense Layers from O(N2) to O(N logN) with Cyclic Sparsely Connected Layers" in proceedings of Design Automation Conference (DAC) 2019
Morteza Hosseini, Hiren Paneliya, Uttej Kallakuri, and Tinoosh Mohsenin "Minimizing Classification Energy of Binarized Neural Network Inference for Wearable Devices" 20th International Symposium on Quality Electronic Design (ISQED). IEEE, 2019.
Morteza Hosseini, Rashidul Islam, Lahir Marni and Tinoosh Mohsenin "MPT: Multiple Parallel Tempering for High-Throughput MCMC Samplers" In Proceedings of the 31st international IEEE System-on-Chip Conference (SOCC), September 2018.
Morteza Hosseini, Rashidul Islam, Amey Kulkarni and Tinoosh Mohsenin, “A Scalable FPGA-based Accelerator for High-Throughput MCMC Algorithms”, In Proceedings of the 25th IEEE FCCM, May 2017.
Hiren Paneliya, Morteza Hosseini, Houman Homayoun, and Tinoosh Mohsenin “CSCMAC – Cyclic Sparsely Connected Neural Network Manycore Accelerator” in proceedings of ISQED 2020.
Hasib-Al Rashid, Nitheesh Manjunath, Hiren Paneliya, Morteza Hosseini, and Tinoosh Mohsenin, “A Low-Power LSTM Processor for Multi-Channel Brain EEG Artifact Detection” in proceedings of ISQED 2020.
Ali Jafari, Morteza Hosseini, Houman Homayoun, and Tinoosh Mohsenin "A Scalable and Low Power DCNN for Multimodal Data Classification" In Proceedings of the ReConfig Conference, December 2018
Mohit Khatwani, Morteza Hosseini, Hiren Paneliya, Tinoosh Mohsenin, “Energy Efficient Convolutional Neural Networks for EEG Artifact Detection” 2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)
Ali Jafari, Morteza Hosseini, Adwaya Kulkarni and Tinoosh Mohsenin, “BiNMAC: Binarized neural Network Manycore Accelerators”, in the 26th Edition of the Great Lakes Symposium on VLSI (GLSVLSI), May 2018.
Lahir Marni, Morteza Hosseini, Tinoosh Mohsenin, “MC3A: Markov Chain Monte Carlo ManyCore Accelerator”, in the 26th Edition of the Great Lakes Symposium on VLSI (GLSVLSI), May 2018
Lahir Marni, Morteza Hosseini, Jennifer Hopp, Pedram Mohseni and Tinoosh Mohsenin, “A Real-Time Wearable FPGA-based Seizure Detection Processor Using MCMC”, In proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018
Siamak Esmaeeli, Morteza Hosseini, Bijan Vosoughi Vahdat, Bizhan Rashidian, “A Multi-Bit Error Tolerant Register File for a High Reliable Embedded Processor”, In Proceeding of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Journal Papers:
Morteza Hosseini, and Tinoosh Mohsenin “Binary Precision Neural Network Manycore Accelerator” in ACM Journal on Emerging Technologies in Computing Systems (JETC) 2020, recently accepted
Nitheesh Manjunath, Aidin Shiri, Morteza Hosseini, Bharat Prakash, and Tinoosh Mohsenin “An Energy Efficient Edge-AI Autoencoder Accelerator for Reinforcement Learning” submitted to IEEE Open Journal of Circuits and Systems 2020, recently accepted
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